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enpirion ? power datasheet EP5348UI 400ma powersoc synchronous buck regulator w ith integrated inductor description the EP5348UI delivers the optimal trade - off between footprint and efficiency. it is a perfect alternative to replace less efficient ldos in space constrained applications that require improved efficiency . the EP5348UI is a 400ma powers o c which integrates mosfet switches, control, compensation, and the magnetics in a micro - qfn package. this highly integrated dcdc solution offers up to 46- points better efficiency than the comparable ldo. a significant reduction i n power loss and improve d thermal s are achieved . it enables e xtended battery life and helps meet energy star requirements. integrated magnetics enables a tiny solution footprint, low output ripple, and high reliability, while maintaining high efficiency. the complete solution size is similar to an ldo and much smaller than a comparable dcdc. features ? integrated inductor technology ? 400ma continuous output current ? 2.0m m x 1.75mm x 0.9mm uqfn package ? small solution footprint ? e fficiency, up to 90 % ? v out range 0.6v to v in ? v d rop_out ? short circuit and over current protection ? uvlo and thermal protection ? ic level reliability in a powers o c solution applications ? applications where poor ldo efficiency creates: o thermal challenges o battery life challenges o failure to meet energy star requirements ? space - constrained applications ? p ortable media players and usb peripherals ep5348 10f 0603 vout pvin agnd v in enable avin pgnd c out v out r a r b vfb 2.2f 0603 c in c avin 0.1f c a figure 1 : typical application schematic 15 25 35 45 55 65 75 85 95 0.0 0.1 0.2 0.3 efficiency (%) load current (a) EP5348UI ldo = 4 www.altera.com/enpirion 05721 october 11, 2013 rev d
e p5348ui ordering information part number package EP5348UI 14- pin qfn t&r evb-ep5348u i ep5 3 48 ui evaluation board pin assignments (top view) figure 2: ep53 48 ui pin out diagram (top view) pin description pin n am e function 1 , 1 3 , 14 nc(sw) no connect ? these pins are internally connected to the common switching node of the internal mosfets. nc (sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage to the device. 2 pgnd power ground. connect this pin to the ground electrode of the input and output filter capacitors. 3, 8, 9 nc no connect: these pins may already be connected inside the devi ce. therefore, they cannot be electrically connected to each other or to any external signal, voltage, or ground. they must however be soldered to the pcb. failure to follow this guideline may result in device damage . 4 v fb feedback pin for external voltage divider network . 5 agnd analog ground. this is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider 6, 7 vout regulated output voltage. refer to application section for proper layout and decoupling. 1 0 enable output enable. enable = logic high; disable = logic low 1 1 avin input power supply for the controller circuitry. connect to vin at a quiet point. 1 2 pvin input voltage for the mosfet switches. pvin avin enable nc nc vout vout nc(sw) nc(sw) EP5348UI 3 1 4 2 5 14 13 6 7 10 9 11 8 12 nc(sw) pgnd nc vfb agnd 2 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability . parameter symbol min m ax units absolute maximum electrical ratings supply voltage ? pvin, avin, vout v in - 0. 3 6.0 v voltage on enable - 0.3 v in + 0.3 v voltage on v fb - 0. 3 2. 7 v esd rating (based on h uman b ody m ode ) 2000 v esd rating (charge device model) 500 v absolute maximum thermal ratings maximum operating junction temperature t j- abs 150 c storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020c 260 c recommended operating conditions parameter symbol min m ax units input voltage range v in 2. 5 5.5 v output voltage range v out 0.6 v in -v do ? v operating ambient temperature t a - 40 +8 5 c operating junction temperature t j - 40 + 125 c ? v do (drop - out voltage) is defined as (i load x dropout resistance) . please see the ec table. thermal characteristics parameter symbol typ units thermal shutdown trip point t j- tp +155 c thermal shutdown trip point hysteresis 15 c thermal resistance: junction to ambient ? 0 lfm ( note 1 ) ja 105 c/w note 1 : based on 2 oz. external copper layers and proper thermal design in line with eia/jedec jesd51 -7 s tandard for high effective thermal conductivity boards. 3 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI electrical characteristics note: t a = - 40c to +85 c unless otherwise noted. typical values are at t a = 25c, vin = 3.6v . c in = 2.2 f 0 603 mlcc , c out = 10 f 0 603 . parameter symbol test conditions min typ m ax units operating input voltage range v in 2. 5 5.5 v under voltage lock - out ? v in rising v uvlo _r 2. 3 v under voltage lock - out ? v in falling v uvlo _f 2.2 v shut - down supply current i sd enable = low 3 a vfb voltage initial accuracy v fb t a = 25 c, v in = 3.6v; i load = 100ma ; 0.8v v out 3.3v 0.588 0.600 0.612 v line regulation ? v out_l ine 2.5 v v in 5.5 v 0.03 %/v load regulation ? 0a i ? v out_temp l - 40 c t a + 85 c 24 ppm / c feedback pin input current i fb note 1 <300 na output current i out 0 400 ma ocp threshold i lim 2.5 v v v out 3.3 v 1.4 a output dropout resistance (note 1) voltage (note 1 ,2 ) r do v do _fl input to output resistance v inmin - v out at full load 520 208 780 312 m ? mv operating output voltage range v out v do = i out * r do 0.6 v in -v do v enable pin logic low v enlo 0.3 v enable pin logic high v enhi 1.4 v enable pin current i enable note 1 <2 00 na operating frequency f osc 9 mhz soft start operation v out rise time t rise from 0 to full output voltage 1.17 1.8 2.43 m sec note s: 1 - parameter guaranteed by design 2 - v do_ fl ( full - load drop - out voltage) is defined as ( maximum i out x dropout resistance) 4 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI typical performance characteristics efficiency vs. load current: v in = 3.3 v, v out (f rom top to bottom) = 2. 5 , 1.8 , 1.2 v efficiency vs. load current: v in = 5.0 v, v out (from top to bottom) = 3.3, 2.5, 1.8, 1.2v output ripple: v in = 3.3 v, v out = 1.0 v , iout = 400ma c in = 2.2 20 30 40 50 60 70 80 90 0.0 0.1 0.2 0.3 0.4 efficiency (%) load current (a) vin = 3.3v vout=2.5 vout=1.8 vout=1.2 top to bottom: 20 30 40 50 60 70 80 90 0.0 0.1 0.2 0.3 0.4 efficiency (%) load current (a) vin = 5.0v vout=3.3v vout=2.5v vout=1.8v vout=1.2v top to bottom: 20 mhz bw limit 500 mhz bw 20 mhz bw limit 500 mhz bw 5 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI load transient: v in = 3.3 v, v out = 1. 0v ch.1: v out , ch. 2: i l oad 0 ? ? ? 6 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI detailed description functional overview the ep5348 ui requires only 2 small mlcc capacitors and a few small - signal components for a complete dc - dc converter solution. the device integrates mosfet switches, pwm controller, gate - drive, part of the loop compensation, and inductor into a tiny 2. 0 mm x 1. 75mm x 0 .9 mm micro - qfn package. advanced package design, along with the high lev el of integration, provides very low output ripple and noise. the ep534 8 ui uses voltage mode control for high noise immunity and load matching to advanced 90nm loads. an external resistor divider is used to program output setting over the 0.6v to v in -v dropout as specified in the electrical characteristics table. the ep534 8 ui provides the industry?s highest power density of any 4 00ma dc - dc converter solution. the key enabler of this revolutionary integration is altera enpirion?s proprietary power mosfet technology. the advanced mosfet switches are implemented in deep - submicron cmos to supply very low switching loss at high switching frequencies and to allow a high level of integration. the se miconductor process allows seamless integration of all switchi ng, control, and compensation circuitry. the proprietary magnetics design provides high - density/high- value magnetics in a very small footprint. altera enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal s olution with assured performance over the entire operating range. protection features include under - voltage lock - out (uvlo), over - current protection (ocp), short circuit protection, and thermal overload protection. integrated inductor the ep534 8 ui utilizes a proprietary low loss integrated inductor. the integration of the inductor greatly simplifies the power supply design process. the inherent shielding and compact construction of the integrated inductor reduces the noise that can couple into the traces of the printed circuit board. further, the package layout is optimized to reduce the electrical path length for the high di/dt currents that are always present in dc- dc converters. the integrated inductor provides the optimal solution to the complexity, o utput ripple, and noise that plague low power dc - dc converter design. control matched to sub 90nm loads the ep5348 ui utilizes a type iii compensation network. voltage mode control is inherently impedance matched to the sub 90nm process technology that is used in today?s advanced ics. voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. the very high switching frequency allows for a very wi de control loop bandwidth and hence excellent transient performance. soft start internal soft start circuits limit the rate of output voltage rise when the device starts up from a power down condition , or when the ?enable? pin is asserted ?high?. digital control circuitry controls the v out rise time to ensure a smooth turn - on ramp. t he ep53 48 ui has a fixed v out turn -on time. therefore, the ramp rate will vary with the output voltage setting. output voltage rise time is given in the electrical characteristics table. excess bulk capacitance on the output of the device can cause an over - current condition at startup. the maximum total capacitance on the output, including the output filter capacito r, and bulk and decoupling capacitance at the load, is given as: c out_total_max = 9.333 x 10 -4 / v out the nominal value for the output filter capacitor is 10uf. see the applications section for more details. over current/short circuit protection the current limit function is achieved by sensing the current flowing through a sense p - 7 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI mosfet which is compared to a reference current. when this level is exceeded the p - fet is turned off and the n - fet is turned on, pulling v out low. this condition is maintained for approximately 0.5ms and then a normal soft start is initiated. if the over current condition still persists, this cycle will repeat. under voltage lockout during initial power up an under voltage lockout circuit will hold - off the switching circuitry until the input voltage reaches a sufficient level to e nsure proper operation. if the voltage drops below the uvlo threshold, the lockout circuitry will disable the switching. hysteresis is included to prevent chattering between states. enable the enable pin provides a means to shut down the converter or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter into normal operation. not e: the enable pin must not be left floating. thermal shutd own when excessive power is dissipated in the chip, the junction temperature rises. once the junction temperature exceeds the thermal shutdown threshold, the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. when the junction temperature decreases by 15c , the device will go through the normal startup process. application information output voltage programming ep5348 10f 0603 vout pvin agnd v in enable avin pgnd c out v out r a r b vfb 2.2f 0603 c in c avin 0.1f c a figure 3 : typical application circuit the EP5348UI uses a simple resistor divider to program the output voltage. referring to figure 3 , use 2 00 k ?, 1% or better for th e upper resistor (r a ). the value of the bottom resistor (r b ) in k? is given as: nominal6.0 ) ( * v vfb vfb v r vfb r out a b = ? = input filter capacitor c in_min = 2.2 f 0603 case size or larger. the input capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch - mode dc - dc converter input filter applic ations. output filter capacitor c out_min = 10uf 0603 + 2.2uf 0603 mlcc when 4.5v v in 5.5v, an d i out > 300ma. c out_min = 10uf 0603 mlcc for all other use cases. however, ripple performance can always be improved by adding a second 2.2uf or 1uf output capacitor for any operating condition. v out has to be sensed at the last output filter capacitor next to the ep534 8 ui. any additional bulk capacitance for load decoupling and byass has to be far enough from the v out 8 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI sensing point so that it does not interfere with the control loop operation. excess total capacitance on the output (output filter + bulk) can cause an over - curren t condition at startup. please see the soft start section under functional overview for the maximum allowable bulk capacitance on the output rail. the output capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielect ric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch - mode dc - dc converter output filter applications. ldo replacement the altera enpirion EP5348UI is a suitable replacement for inefficient ldos and c an be used to augment the ldos in a pmu with min imum footprint impact. this integrated dcdc solution offers significantly better efficiency , and significant reduction i n power loss . the resulting i mprove d thermals and extended battery l ife h elps m eet energy star requirements. the total solution size is 25% smaller than a comparable ldo and half the footprint of a comparable dcdc . as the table below shows, EP5348UI provides the optimal trade - off between footprint and efficiency when compared to a tradition al ldo: power - up /down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power down, the avin should not be powered down before the pvin. tying pvin and avin or all three pins (avin, pvin, enable) together during power up or power down meets these requirements . pre - bias start - up the ep5 3 48u i does not support startup into a pre - biased condition. be sure the output capacitors are not charged or the output of the ep53 48u i is not pre - biased when the ep53 48u i is first enabled. layout recommendations f igure 4 : top pcb layer critical components and copper for minimum footprint figure 5 : bottom pcb layer critical components (r a , r b , c a ) & copper for minimum footprint vin (v) vout (v) load (ma) eff dcdc eff ldo ploss dcdc (mw) ploss ldo (mw) power saved (mw) 5.0 1.2 400 70.4% 24.0% 202 1520 1318 5.0 1.8 400 76.4% 36.0% 222 1280 1058 5.0 2.5 400 81.6% 50.0% 225 1000 775 5.0 3.3 400 87.7% 66.0% 185 680 495 3.3 1.2 400 77.1% 36.4% 143 840 697 3.3 1.8 400 83.3% 54.5% 144 600 456 3.3 2.5 400 88.2% 75.8% 134 320 186 9 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI figure s 4 and 5 show critical pcb top and bottom layer components and traces for a minimum - footpint recommended ep5348 layout with enable tied to v in . alternate enable configurations need to be connected and routed according to specific customer application. this layout consists of four layers. for the other 2 layers and the exact dimensions, please see the gerber files a t www.altera.com/enpirion . the recommendations given below are general guidelines. customers may need to adjust these according to their own layout and manufacturing rules. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the e p5348u i package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the e p5348ui should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and the input/output capacitors. please see the gerber files at www.altera.com/enpirion . recommendation 3 : multiple small vias should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias along the edge of the gnd copper closest to the +v copper. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. see figure 4 . if the two vias cannot be put under c in or c out , then put two vias right after the capacitors next the v in and v out vias. recommendation 4 : as figure 5 shows, r a , r b , and c a have been placed on the back side to minimize the footprint. these components also need to be close to the vfb pin (see figure s 3 , 4 and 5 ). the vfb pin is a high - impedance, sensitive node. keep any trace connected to this node as short and thin as possible. whenever possible, connect r b directly to the agnd pin instead of going through the gnd plane. in the layout shown above, r b goes to the via next to agnd pin using a dedicated trace on layer 3 not shown here. please see the gerber files at www.altera .com/enpirion . recommendation 5 : avin is the power supply for the small - signal control circuits. it should be connected to the input voltage at a quiet point. in figure 4 this connection is made at the vias just before c in . there is an additional decoupling capacitor c avin for avin whic h is connected between the device pin and the gnd plane. recommendation 6 : the via to the right of pin 2 underneath the device helps to minimize the parasitic inductances in the input and output loop ground connections. recommendation 7 : the top layer 1 metal under the device must not be more than shown in figure 4 . as with any switch - mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. recommendation 8 : the v out sense point should be jus t after the last output filter capacitor. keep the sense trace short in order to avoid noise coupling into the node. 10 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI recommended pcb footprint figure 6 : en53 48u i package pcb footprint package and mechanical figure 7 en53 48u i package dimensions dimensions in mm 11 www.altera.com/enpirion 05721 october 11, 2013 rev d
EP5348UI contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408-544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for produc t s o r se rvi c e s. 12 www.altera.com/enpirion 05721 october 11, 2013 rev d

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